1. Field of the Disclosure
The present invention relates to a shift register in which a pull-up switching device is turned off positively in a period in which no scan pulse is forwarded for securing drive stability and prevents a picture quality from becoming poor.
2. Discussion of the Related Art
Recently, a GIP (Gate In Panel) type display device is introduced, in which a gate driving circuit is built in a panel thereof for reducing volume and weight of the display device and saving production cost.
In the GIP type display device, the gate driving circuit is built in a non-display region of the panel by using an amorphous silicon thin film transistor (Hereafter call as TFT). The gate driving circuit has the shift register for supplying a scan pulse to a plurality of gate lines in succession. The shift register has a plurality of stages for forwarding the scan pulse by using a clock pulse from a timing controller, each with a pull up TFT for forwarding the clock pulse as the scan pulse depending on a signal state of a set node.
The pull up TFT is turned on only in a portion of one frame period, and turned off in most of the period except the portion of the period. According to this, each of the stages forwards the scan pulse only in the portion of the one frame period, and a low voltage in rest of the period.
In the meantime, if the pull up TFT is turned on in the period in which no scan pulse is forwarded, an output voltage of a stage which is required to sustain the low voltage becomes unstable, which is likely to cause a poor picture quality. Therefore, each of the stages has a plurality of control TFTS for discharging potential of the set node to the low state in the period in which no scan pulse is forwarded.
The plurality of control TFTS includes a first control TFT for discharging the set node in response to a start pulse, a second control TFT for discharging the set node in response to the scan pulse provided from a next state, and a third control TFT for discharging the set node in response to the clock pulse.
In the meantime, there is a blank period between frames, in which no clock pulse is forwarded. The shift register has a problem in that many control TFTS do not operate in the blank period, causing the set node to float. Particularly, all of the first to third control TFTS do not operate in a period within the blank period after the start pulse is forwarded, to float the set node. Once the set node is floated, a leakage current is liable to generate in the pull up TFT due to coupling, and the output voltage of the stage becomes unstable, resulting in a poor picture quality.